Esteve Amat Bertran

La paciència és la mare de la ciència

Publications

List of journal publications where I have collaborated:

[29] P.Pouyan, E.Amat and A.Rubio; “Memristive Crossbar Memory Lifetime Evaluation and Reconfiguration Strategies”, IEEE Transactions on Emerging Topics in Computing, vol. xx, pp. yy-yy, 2016, accepted for their publication.

[28] F.Berthier, E.Beigne, F.Heitzmann, O.Debicki, J-F.Christmann, A.Valentian, O.Billont, E.Amat, D.Morche, S.Chairat and O.Sentieys; “UTBB FDSOI suitability for IoT applications: Investigations at device, design and architectural levels”, Soli-State Electronics, vol. xx, pp. yy-yy, 2016, accepted for their publication.

[27] E.Amat, A.Calomarde, F.Moll, R.Canal and A.Rubio; “Variability Impact on On-Chip Memory Data Paths”, Journal of Low Power Electronics, vol. 11 (2), pp. 250-255, 2015.

[26] E.Amat, A.Calomarde, F.Moll, R.Canal and A.Rubio; “Feasibility of the embedded DRAM cells implementation with FinFET devices”, IEEE TRANSACTIONS ON COMPUTERS, 2015. (10.1109/TC.2014.2375204)

[25] P.Pouyan, E.Amat and A.Rubio; “Adaptive Proactive Reconfiguration: A Technique for Process Variability and Aging Aware SRAM Cache Design”, IEEE TRANSACTIONS ON VLSI, vol. 23 (9), pp. 1951-1955, 2014.  (10.1109/TVLSI.2014.2355873)

[24] A. Calomarde, E.Amat, F. Moll, J. Vigara and A.Rubio; “A SET and Noise Fault Tolerant Circuit Design Technique: Application to 7nm FinFET Microelectronics Reliability”, MICROELECTRONICS RELIABILITY, vol. 54(4), pp. 738-745, 2014.

[23] E.Amat, C.G.Almudéver, N.Aymerich, R.Canal and A.Rubio; “Suitability of the FinFET 3T1D cell beyond 10nm”, IEEE TRANSACTIONS ON NANOTECHNOLOGY, vol. 13(5), pp. 926-932, 2014.

[22] E.Amat, A.Calomarde, C.G.Almudéver, N.Aymerich, R.Canal and A.Rubio; “Impact of FinFET and III-V/Ge technology on logic and memory cell behavior”, IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, vol. 14(1), pp. 344-350, 2014.

[21] E.Amat, E. Amatllé, S.Gómez, N.Aymerich, C.G.Almudéver, F.Moll and A.Rubio; “Systematic and random variability analysis of two different 6T-SRAM layout topologies”, Microelectronics Journal, vol. 44 (9), pp. 787-793, 2013.

[20] E.Amat, C.G.Almudéver, N.Aymerich, R.Canal and A.Rubio; “Impact of FinFET technology introduction in the 3T1D-DRAM memory cell”, IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, vol. 13 (1), pp. 287-292, 2013.

[19] E. Amat, T. Kauerauf, R. Degraeve, R. Rodríguez, M. Nafría, X. Aymerich and G. Groeseneken; “A comprehensive study of Channel Hot-Carrier degradation in short channel MOSFETs with high-k dielectrics”, MICROELECTRONIC ENGINEERING, vol. 103, pp. 144-149, 2013.

[18] E.Amat, C.G.Almudéver, N.Aymerich, R.Canal and A.Rubio; “Variability mitigation mechanisms in scaled 3T1D DRAM memories to 22nm and beyond”, IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY vol. 13 (1), pp. 103-109, 2013.

[17] N.Ayala, J.Martin-Martinez, E.Amat, MB. Gonzalez, P. Verheyen, R.Rodriguez, M.Nafria, X.Aymerich and E.Simoen; “NBTI related time-dependent variability of mobility and threshold voltage in pMOSFETs and their impact on circuit performance”, MICROELECTRONIC ENGINEERING, Vol. 88, pp. 1384-1387, 2011.

[16] E. Amat, T. Kauerauf, R. Degraeve, R. Rodríguez, M. Nafría, X. Aymerich and G. Groeseneken; “Gate voltage influence on the Channel Hot-Carrier degradation of high-k based devices”, IEEE TDMR, Vol. 11 (1), pp. 92-97, 2011.

[15] E. Amat, R. Rodríguez, M.B. Bargallo, J. Martin-Martinez, M. Nafría, X. Aymerich, P.Verheyen and E. Simoen; “CHC degradation of strained devices based on SiON and high-k gate dielectric materials”, Microelectronic Engineering, Vol. 88 (7), pp. 1408-1411, 2011.

[14] E. Amat, J. Martin-Martinez, M.B. Bargallo, R. Rodríguez, M. Nafría, X. Aymerich, P. Verheyen and E. Simoen; “Processing dependences of channel hot-carrier degradation on strained-Si p-channel metal-oxide semiconductor field-effect transistors”, Journal of vacuum science & technology, Vol. 29 (1), 2011.

[13] E. Amat, T. Kauerauf, R. Degraeve, R. Rodríguez, M. Nafría, X. Aymerich and G. Groeseneken; “Channel Hot-Carrier degradation in pMOS and nMOS short channel transistors with high-k dielectric stack”, Microelectronic Engineering, Vol. 87 (1), pp. 47-50, 2010.

[12] J. Martin-Martinez, E. Amat, M.B. Gonzalez, P. Verheyen, R. Rodríguez, M. Nafría, X. Aymerich, and E. Simoen; “SPICE modelling of hot-carrier degradation in Si1-xGex S/D and HfSiON based pMOS transistors”, Microelectronics Reliability, pp. 1263-1266, 2010.

[11] E.Amat, T.Kauerauf, R.Degraeve, R.Rodríguez, M.Nafría, X.Aymerich and G.Groeseneken; “Simulation of the hot-carrier degradation in short channel transistors with high-K dielectric”, International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, 2010.

[10] E. Amat, T. Kauerauf, R. Degraeve, A. De Keergister, R. Rodríguez, M. Nafría, X. Aymerich and G. Groeseneken; “Channel Hot-Carrier degradation in short-channel transistors with high-k/metal gate stacks”, IEEE TDMR, Vol. 9 (3), pp. 425-430, 2009.

[9] E. Amat, T. Kauerauf, R. Degraeve, R. Rodríguez, M. Nafría, X. Aymerich and G. Groeseneken; “Competing degradation mechanism in short-channel transistors under Channel Hot-Carrier stress at elevated temperatures”, IEEE TDMR, Vol. 9 (3), pp. 454-458, 2009.

[8] D. Maji, F. Cruppi, E. Amat, E. Simoen, B. De Jaeger, D. Brunco, C. Manoj, V. Rao, P. Magnone, G. Giusi, C. Pace, L. Pantisano, J. Mitard, R. Rodríguez and M. Nafría; “Understanding and optimization of Hot-Carrier reliability in germanium-on-silicon pMOSFETs”, IEEE TED, Vol. 56 (5), pp. 1063-1069, 2009.

[7] A. Gasperini, E. Amat, M. Porti, J. Martin-Martinez, M. Nafría, X. Aymerich and A. Paccagnella; “Effects of the localization of the charge in nanocrystal memory cells”, IEEE TED, Vol. 56 (5), pp. 2319-2326, 2009.

[6] J. Martin-Martinez, S. Gerardin, E. Amat, R. Rodriguez, M. Nafría, X. Aymerich, A. Paccagnella and G. Ghidini; “Channel Hot-Carrier degradation and Bias Temperature instabilities in CMOS inverters”, IEEE TED, Vol. 56 (9), pp. 2155-2159, 2009.

[5] A.Gasperin, E.Amat, J.Martín-Martínez, M.Porti, M.Nafría and A.Paccagnella; “Peculiar characteristics of nanocrystal memory cells programming window”, Journal of Vacuum Science & Technology B, Vol. 27, pp. 512-516, 2009.

[4] E.Amat, R.Rodríguez, M.Nafría and X.Aymerich; “Channel hot-carrier degradation under AC stress in short channel nMOS devices with high-K gate stacks”, Microelectronic Engineering, Vol. 86, pp. 1908- 1910, 2009.

[3] L.Aguilera, E.Amat, R.Rodríguez, M.Porti, M.Nafría and X.Aymerich; “Analysis of the degradation of HfO2/SiO2 gate stacks using nanoscale and device level techniques”, Microelectronic Engineering, Vol. 84, pp. 1618-1621, 2007.

[2] E. Amat, R. Rodríguez, M. Nafría, X. Aymerich and J.H. Stathis; “Influence of the SiO2 layer thickness on the degradation of HfO2 / SiO2 stacks subjected to static and dynamic stress conditions”, Microelectronics Reliability, Vol. 47 (4-5), pp. 544-547, 2007.

[1] J. Garcia-Garcia, F. Martin, F. Falcone, J. Bonache, J.D. Baena, I. Gil, E. Amat, T. Lopetegui, M.A.G. Laso, J.A. Marcotegui Iturmendi, M. Sorolla and R. Marqués; “Microwave filter with improved stopband based on sub-wavelength resonator”, IEEE Transactions on Microwave theory and techniques, Vol. 53 (6), pp. 1997, 2005.

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