Esteve Amat Bertran

La paciència és la mare de la ciència

Conferences

List of international conferences where I have presented contributions:

[43] E. Amat, A. Calomarde, R. Canal and A.Rubio; “Suitability of FinFET introduction into eDRAM cells for operate at sub-threshold level”, PATMOS, Tessaloniki (Greece), Sept 2017.

[42] E. Amat, M. Fernandez-Regulez, M. Lorenzoni, L. Evangelio, J.Bausells and F.Perez-Murano; “”Exploring strategies to contact 3D nano-pillars below 100 nm”, MNE, Braga (Portugal), Sept 2017.

[41] E. Amat, J.Bausells and F.Perez-Murano; “Exploring an improvement SET-FET hybrid behavior by using different FET types”, MNE, Vienna (Austria), Sept 2016.

[40] A.Calomarde, E. Amat, P.Moll, F.Gamiz and A. Rubio; “Active Charge Collection Strategy for Radiation Environment at Device Level”, RADECS, Bremen (Germany), Sept 2016.

[39] P. Pouyan, E. Amat and A. Rubio; “RRAM Variability and its Mitigation Schemes”, VARI, Bremen (Germany), Sept 2016.

[38] P. Pouyan, E. Amat and A. Rubio; “Monitoring SRAM BTI Degradation By Current-based Tracking Technique”, NEWCAS, Vancouver (Canada), Aug 2016.

[37] P. Pouyan, E. Amat and A. Rubio; “Insights to the memristive memory cell from a reliability perspective”, Memrisys, Paphos (Cyprus), Nov 2015.

[36] E. Beigne, J.F. Chrsitmann, A. Valentian, O. Billoint, E. Amat and D. Morche, “UTBB FDSOI tecnology flexibility for ultra low power Internet-of-Things applications”, ESSDERC, Graz (Austria), Sept 2015.

[35] P. Pouyan, E. Amat and A. Rubio; “Memristive crossbar design and test in non-adaptive proactive reconfiguration”European Conference on Circuit Theory and Design (ECCTD), Trondheim (Norway), August 2015.

[34] P. Pouyan, E. Amat and A. Rubio; “Analysis and design of an adaptive proactive reconsiguration approach for memristive crossbar memories”, IEEE / ACM International Symposium on nanoscale architectures (Nanoarch), Boston (USA), July 2015.

[33] P. Pouyan, E. Amat and A. Rubio; “Statistical lifetime analysis of memristive crossbar matrix”, IEEE / ACM International Symposium on nanoscale architectures (Nanoarch), Boston (USA), July 2015.

[32] E. Amat, J.F. Christmann, O. Billoint, I. Miro and E. Beigne; “Exploring FDSOI Devices for Asynchronous Full-Adders at Sub-Threshold Level”, Electrochemical Society meeting (ECS), Chicago (USA), May 2015.

[31] P.Pouyan, E. Amat and A. Rubio; Statistical Lifetime Analysis of Memristive Crossbar Matrix, Design & Technology of Integrated Systems (DTIS), Naples (Italy), April 2015.

[30] P.Pouyan, E. Amat and A. Rubio; Statistical Lifetime Analysis of Memristive Crossbar Matrix, Design, Automation & Test  in Europe (DATE), Grenoble (France), March 2015.

[29] P.Pouyan, E. Amat and A. Rubio; “Reliability challenges in design of memristive memories”, 5th European Workshop on CMOS Variability (VARI), Palma de Mallorca (Spain), October 2014.

[28] E. Amat, A.Calomarde, R. Canal and A. Rubio; “Variability impact on on-chip memory data paths”5th European Workshop on CMOS Variability (VARI), Palma de Mallorca (Spain), October 2014.

[27] E. Amat, C.G. Almudéver, N. Aymerich, R. Canal and A. Rubio; “FinFET introduction in 3T1D-DRAM memory cells”, 28th Conference on Design of Circuits and Integrated Systems (DCIS), Donosti (Spain), November 2013.

[26] E. Amat, A.Calomarde, C.G. Almudéver, N. Aymerich, R. Canal and A. Rubio; “FinFET and III-V/Ge technology impact on 3T1D cell behavior”, Intel Ireland Research Conference (IIRC), Dublin (Ireland), November 2013.

[25] E. Amat, C.G. Almudéver, N. Aymerich, R. Canal and A. Rubio; Variability robustness enhancement for 7nm FinFET 3T1D-DRAM cells, IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Ohio (USA), August 2013.

[24] A. Calomarde, E. Amat, F. Moll and A. Rubio; “A Single Event Transient Hardening Circuit Design Technique Based on Strengthening”, IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Ohio (USA), August 2013.

[23] E.Amat, A. Calomarde and A. Rubio; “Reliability Study on Technology Trends Beyond 20nm”, IEEE International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES), Gdynia (Poland), June 2013.   !!! Outstanding paper !!!

[22] A. Bayerl, M. Porti, J. Martin-Martínez, R. Rodriguez, V. Velayudhan, M. B. Gonzalez, E. Amat, M. Nafria, E. Simoen and X. Aymerich; “Channel hot-carriers degradation in MOSFETs: A Conductive AFM study at the nanoscale”, IEEE International Reliability Physics Symposium (IRPS), Moterrey (USA), 2013.

[21] P.Pouyan, E.Amat, F. Moll and A.Rubio; “Design and Implementation of an Adaptive Proactive Reconfiguration technique in SRAM Caches”; Design, Automation & Test in Europe Conference & Exhibition (DATE), Grenoble (France), 2013.

[20] E. Amat, C.G. Almudéver, N. Aymerich, R. Canal and A. Rubio; “Mitigation strategies of the variability in 3T1D-DRAM cell memories scaled beyond 22nm”, 27th Conference on Design of Circuits and Integrated Systems (DCIS), Avignon (France), pp. 386-390, 2012.     !!!! Best paper !!!!

[19] E. Amat, C.G. Almudéver, N. Aymerich, R. Canal and A. Rubio; “SOI/Bulk FinFET introduction in 3T1D-DRAM cell”, IEEE International Conference on Solid-State and Integrated Circuits (ICSICT), pp. 984-986, Xi’an (China), 2012.

[18] E. Amat, A. Asenov, R. Canal, B. Cheng, J. Cruz, Z. Jaksic, M. Miranda, A. Rubio and P. Zuber ; “Analysis of FinFET technology on memories”, 18th IEEE International On-Line Testing Symposium (IOLTS), pp. 169, 2012.

[17] P.Pouyan, E.Amat and A.Rubio; “SRAM lifetime improvement by using adaptive proactive reconfiguration”, Mixed design of Integrated circuits and systems (MIXDES), 2012.

[16] E. Amat, C.G. Almudéver, N. Aymerich, R. Canal and A. Rubio; “Strain relevance on the improvement of the 3T1D cell performance”, International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES), Varsaw (Poland), 2012.

[15] P.Pouyan, E.Amat and A.Rubio; “Process variability-aware proactive reconfiguration technique for mitigating aging effects in nanos scale SRAM lifetime”, IEEE VLSI Test Symposium, pp. 240-245, Hawaii (USA), 2012.

[14] P.Pouyan, E.Amat and A.Rubio; ”Proactive Reconfiguration,a methodology for extending SRAM lifetime”, VAMM Workshop in DATE, Dresden (Germany), 2012.

[13] E. Amat, R. Rodríguez, M.B. Gonzalez, J. Martin-Martinez, M. Nafría, X. Aymerich, P. Verheyen and E. Simoen; “CHC degradation of strained devices based on SiON and high-k gate dielectric materials”, Conference on Insulating Film on Semiconductors (INFOS), Bratislava (Slovakia), 2011.

[12] J.Martin-Martinez, E.Amat, MB. Gonzalez, P. Verheyen, R.Rodriguez, M.Nafria, X.Aymerich and E.Simoen; “Aging mechanisms in strained Si/high-k based pMOS transistors. Implications in CMOS circuits”, Conferencia de Dispositivos Electrónicos (CDE), Valladolid (Spain), 2011.

[11] E. Amat, R. Rodríguez, M.B. Gonzalez, J. Martin-Martinez, M. Nafría, X. Aymerich, V. Machkaoutsan, M. Bauer, P. Verheyen and E. Simoen; “Channel Hot-Carrier degradation on strained MOSFET with embedded SiGe or SiC Source/Drain”, IEEE International Conference on Solid-State and Integrated Circuits (ICSICT), pp. 1648-1650, Shangai (China), 2010.

[10] E. Amat, R. Rodríguez, M. Nafría, X. Aymerich T. Kauerauf, R. Degraeve and G. Groeseneken; “New insights into the wide ID range channel hot-carrier degradation in high-k based devices”, IEEE International Reliability Physics Symposium (IRPS), pp. 1028-1032, Montreal (Canada), 2009.

[9] E. Amat, R. Rodríguez, M. Nafría and X. Aymerich; “Channel Hot-Carrier degradation under AC stress in short channel nMOS devices with high-k gate stacks”, Conference on Insulating Film on Semiconductors (INFOS), Cambridge (UK), 2009.

[8] E. Amat, T. Kauerauf, R. Degraeve, R. Rodríguez, M. Nafría, X. Aymerich and G. Groeseneken; “Simulation of the hot-carrier degradation in short channel transistors with high-k dielectric”, Spanish Conference on Electron Devices (CDE), Santiago de Compostela (Spain), 2009.

[7] E. Amat, T. Kauerauf, R. Degraeve, A. De Keergieter, R. Rodríguez, M. Nafría, X. Aymerich and G. Groeseneken; “Channel Hot-Carrier degradation under static stress in short channel transistors with high-k/metal gate stacks”, International Conference on Ultimate Integration of Silicon (ULIS), pp. 103-106, Udine (Italy), 2008.

[6] L.Aguilera, E.Amat, M.Porti, R.Rodríguez, M.Nafria and X.Aymerich; “Nanoscale and device level degradation of Hf/SiO2 gate stacks in CMOS electronic nanodevices”, Conferencia de Dispositivos Electrónicos, Barcelona (Spain)2007.

[5] A.Gasperin, E.Amat, J.Martin-Martínez, M.Porti, M.Nafría and A.Paccagnella; “Peculiar characteristics of nanocrystal memory cells programming window”, Workshop on Dielectrics in Microelectronics (WODIM), Berlin (Germany), 2006.

[4] L.Aguilera, E.Amat, R.Rodríguez, M.Porti, M.Nafria, X.Aymerich; “Analysis of the degradation of Hf/SiO2 gate stacks using nanoscale and device level techniques”, MNE, Barcelona (Spain), 2006.

[3] E.Amat, R.Rodríguez, M.Porti, L.Aguilera, J.Boix, R.Fernandez, J.Martin, M.Nafria, X.Aymerich; “Degradación de stacks de puerta HfO2 / SiO2 en nanodispositivos CMOS”, XXII Trobades científiques de la mediterrània. Nanociència i nanotecnologia, Palma de Mallorca (Spain)2006.

[2] L. Aguilera, E. Amat, R. Rodríguez, M. Nafria, Xavier Aymerich; “Nanoscale and device level degradation of Hf/SiO2 gate stacks in CMOS electronic nanodevices”, NanoSpain, 2006.

[1] E. Amat, R. Rodríguez, M. Nafría, X. Aymerich and J.H. Stathis; “Influence of the SiO2 layer thickness on the degradation of HfO2 / SiO2 stacks subjected to static and dynamic stress conditions”, 14th Workshop on dielectrics in Microelectronics (WODIM), June 26-28, Catania (Italy), 2006.
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